The present invention relates to semiconductor memory devices, and more particularly, to dynamic random access memory (DRAM) devices.
The demand for DRAM devices continues to rise, particularly for large capacity DRAM devices. However, chip size limitations generally limit the capacity of the DRAM devices. As the chip size increases, to provide for a greater capacity, the number of chips per wafer in the manufacturing process decreases. Furthermore, the manufacturing yield for the DRAM devices may decrease. Therefore, various approaches have been proposed for increasing the number of memory cells per wafer by modifying cell layout to decrease the cell area per memory cell. In some of these proposed approaches, a conventional 8F2 layout is changed to a 6F2 layout.
FIG. 1 is a layout view showing a conventional DRAM device having 8F2 layout and diagonal active regions. Active regions 102 defined by an isolation region 101 are repeatedly disposed with a predetermined spacing. The active regions 102 have a shape that will be referred to herein as a two-curved-end bar. The active regions 102 may have other shapes. The active regions 102 are illustrated as slanted with reference to a horizontal direction X. The slanted active regions 102 are sometimes referred to as diagonal active regions. Word lines 103, comprising gate conductive layers, extend linearly in a vertical direction Y in a striped pattern. Bit lines 104, comprising bitline conductive layers, extend linearly in the horizontal direction X in a striped pattern. Two word lines 103 and one bit line 104 intersect each other in a single active region 102. In a DRAM having such a structure, a unit cell UC1 has horizontal and vertical lengths of 4F and 2F, respectively, in terms of a minimum line width F. Therefore, an area of the unit cell UC1 is 8F2. There are two unit cells UC1 in a single active region 102.
FIG. 2 is a layout view showing a conventional DRAM device having an 8F2 layout and split active regions. Active regions 202 have a shape of a two-curved-end bar. The active regions 202 lie in the horizontal direction X. Upper and lower adjacent active region 202 are disposed in a zigzag pattern. Each of word lines 203 extend in the vertical direction Y in a striped pattern and overlap with at least one of the adjacent active regions 202 disposed in a zigzag pattern. Bit lines 204 extend in the horizontal direction X in a striped pattern between the adjacent active regions 202 disposed in a zigzag pattern. In a DRAM having the illustrated structure of FIG. 2, a unit cell UC2 has horizontal and vertical lengths of 4F and 2F, respectively, in terms of a minimum line width F. Therefore, an area of the unit cell UC2 is also 8F2. Unlike the DRAM device having diagonal active regions as illustrated in FIG. 1, there is only a single unit cell UC2 in a single active region 202.
DRAM devices having a 6F2 layout have been proposed to replace the conventional DRAM having an 8F2 layout. In a DRAM device having a 6F2 layout, a unit cell generally has horizontal and vertical lengths of 3F and 2F, respectively, in terms of a minimum line width F. Therefore, an area of the unit cell is 6F2, so that the degree of integration of the DRAM device can be increased. DRAM devices having a 6F2 layout typically have diagonal active regions. In general, there are two unit cells in a single active region. The degree of integration of a DRAM device having a 6F2 layout can typically be increased in comparison to a DRAM having an 8F2 layout. However, it may be difficult to form the diagonal active regions with a high degree of integration in a DRAM device having a 6F2 layout. For example, a mask for the diagonal active regions is typically implemented by forming a large number of small segments. This is generally a very time-consuming and high-cost process. Moreover, for an asymmetrical layout, the associated patterning process using photolithography may be very difficult.